1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices in which a semiconductor substrate is exposed so as to form an interconnection pattern for forming a desired circuit.
2. Description of Related Art
Nowadays, IC""s (Integrated Circuit) having electronic circuits, which are incorporated in every electronic apparatus, are essential for minimization and upgrading of electronic apparatus. A semiconductor substrate consisting of a material such as silicon is exposed to a light with interposition of an exposure pattern for forming a predetermined circuit to form interconnection patterns, and is processed through development and other prescribed processes to manufacture an IC. In manufacturing an interconnection pattern, it is required that the correction magnitude of the variation of the focus position (referred to as focus hereinafter) that is the distance to a semiconductor substrate and the sensitivity variation (the sensitivity is corrected by correcting, for example, exposure), which vary during manufacturing, are fed back to an exposure apparatus in order to adjust the interconnection width of interconnection patterns to the target interconnection width, and thus the exposure condition is optimized.
A conventional method in which test samples are subjected to exposure before manufacturing of the IC as the product to determine the exposure condition for exposure of the interconnection pattern for forming a circuit has been used. In this method, it is needed that the focus and sensitivity variation with step-wise variation of the focus and exposure energy (referred to as exposure quantity) of an exposure apparatus is calculated previously to calculate the optimal correction magnitude as the preparative work (referred to as condition prediction). The condition prediction leads to increased work and causes poor TAT (Turn Around Time).
Another exposure method in which the above-mentioned condition prediction is not required to avoid poor TAT has been known. In this method, the exposure quantity and the interconnection width after exposure of the interconnection pattern (finished) are monitored on every lot manufactured in the past in order to predict the exposure condition of semiconductor devices manufactured under control of sensitivity variation trend, and the exposure condition is thereby determined.
FIG. 12 is a flow chart for describing yet another conventional exposure method.
In the conventional exposure method, first a predetermined exposure pattern having a prescribed interconnection pattern is exposed on a semiconductor substrate (step ST21). The interconnection width of the exposed interconnection pattern is measured (step ST22). The difference between the target interconnection width and the actual resultant interconnection width is detected to determine the sensitivity deviation (step ST23). If no sensitivity deviation is detected (OK), then the execution is brought to an end (step ST26), and otherwise if sensitivity deviation is detected, then the exposure correction magnitude xcex94E is calculated from the difference detected (step ST24). The exposure quantity is corrected based on the exposure correction magnitude xcex94E (step ST25).
In the trend control according to the above-mentioned exposure method, when a variation of the interconnection width off the specification is detected in the trend control of the sensitivity variation (for example, lots 6 and 10 in FIGS. 11A and 11B), to fit it to the target interconnection width (target interconnection width shown in FIG. 14) that is the target of the interconnection pattern after exposure, the exposure quantity is calculated from the exposure quantity versus interconnection width characteristic curve which has been obtained previously. This correction value is fed back to the exposure apparatus to vary the exposure condition. Also in the case in which the wring width of manufactured semiconductor devices is measured to perform trend control for fine correction even if variation of the interconnection width of interconnection pattern after exposure off the specification is detected, correction is performed based on the exposure quantity.
However, because the deviation in interconnection width is corrected only by varying the exposure quantity in this exposure method, the deviation in focus is not corrected, and it causes the following problem.
FIG. 13A is a finished interconnection width characteristics of an interconnection pattern for simultaneous variation of the sensitivity and focus. FIG. 13B is a finished interconnection width characteristics after correction of an interconnection pattern obtained when the deviation is corrected only by varying exposure quantity for simultaneous variation of the sensitivity and focus.
In FIG. 13A and FIG. 13B, the axis of abscissa represents the focus and the axis of ordinate represents the interconnection width (line width).
Correction according to the conventional exposure method shown in FIG. 12 shows the result that the actual line width is within the allowance of the target line width for sparse pattern, but the actual line width exceeds the allowable upper limit of the line width specification for uncontrolled dense pattern because the correction depends on only exposure quantity xcex94E. Though the actual line width is within the allowance for the sparse pattern, the focus versus interconnection width characteristics fluctuates and the variation of focus affects the stability of the exposed interconnection width significantly because the focus deviation remains as it was.
The interconnection width characteristics j and k represents the interconnection width characteristics of two interconnection patterns which are different in the density of finished interconnection width. The interconnection width characteristics j represents the interconnection width characteristics of the sparse interconnection pattern, on the other hand, the interconnection width characteristics k represents the interconnection width characteristics of the dense interconnection pattern.
On a semiconductor substrate which is a component of a semiconductor device, various interconnection patterns different in the line density are formed actually. Therefore, the interconnection width characteristics versus focus depends on the line density of the interconnection pattern.
When a exposure pattern served as a transfer pattern for forming a circuit on a semiconductor substrate by exposure is copied on a semiconductor substrate by exposure, the focus versus interconnection width characteristics changes gradually from the mountain-shape to the valley-shape as shown in the order from FIG. 5B, to FIG. 6B, and FIG. 7B as the interconnection pattern becomes denser as shown in the order from FIG. 5A, to FIG. 6A, and FIG. 7A.
In the case that the focus F deviates from the ideal focus F1 as shown in FIG. 13A, though the position on X-axis at the inflection point of the interconnection width characteristics corresponds to the ideal focus F1, the focus which is actually exposed to a light in manufacturing process corresponds to the vertical dotted line F (the difference xcex94F between the focus F shown with the dotted line and the above-mentioned ideal focus F1 is referred to as focus deviation hereinafter).
The above-mentioned situation causes the difference in finished interconnection width after exposure between the sparse interconnection width characteristics and the dense interconnection width characteristics. Correction of the exposure quantity by exposure correction magnitude xcex94E only moves the interconnection width characteristics k and the interconnection width characteristics j vertically (in the direction of interconnection width) along the axis of ordinate in the graph shown in FIG. 13A, and it is impossible to solve the finished interconnection width difference due to the above-mentioned focus deviation xcex94F.
In this exposure method, only the interconnection width characteristics j is controlled as shown in FIG. 13B. Therefore in some cases, the pattern of interconnection width characteristics k exceeds the USL (USL is used as an abbreviation of upper specification limit of the interconnection width. LSL is used as an abbreviation of lower specification limit of the interconnection width.) Outside the specification after correction, and defective products are manufactured.
Another problem of focus deviation xcex94F is the area W1 (the interconnection pattern characteristics j is inclined steeply) where the variation in the interconnection width to the variation in the focus is larger than that at the above-mentioned inflection point for the ideal focus F1 though the interconnection width characteristics j is within the target line width as shown in FIG. 13B, and the stability of the interconnection width of the exposed interconnection pattern to the variation in focus is poor. Problems described herein above arise from the difficulty in separate correction of the variation in focus F and the variation in sensitivity.
It is the object of the present invention to solve the above-mentioned problems by providing a method for manufacturing semiconductor devices in which the focus position variation and the sensitivity variation are separated and detected respectively without previous calculation of the optimal correction magnitude for obtaining the target-sized interconnection width of interconnection pattern of semiconductor devices to correct the exposure condition and to secure the exposure of the interconnection pattern of the target interconnection width, and further the trend of the focus position and the sensitivity is controlled accurately to secure the accurate exposure of the interconnection patterns which are different in the line density of the interconnection pattern and to improve the production efficiency of the semiconductor device.
The above-mentioned object of the present invention is achieved by applying a method for manufacturing semiconductor devices in which exposure is performed to form an interconnection pattern of the predetermined circuit on a semiconductor substrate with correction of the exposure condition comprising the first step for exposing on the semiconductor substrate the first exposure management pattern having interconnection patterns which are disposed with a certain interval and disposed so that the variation in the exposure quantity on the semiconductor substrate affects the interconnection width but the variation in focus position which occurs when the semiconductor substrate is exposed does not affect the interconnection width, and the second exposure management pattern having interconnection patterns which are disposed with a certain interval different from that of the first exposure management pattern and disposed so that both focus variation and exposure quantity variation affect the interconnection width, the second step for measuring the interconnection width of the interconnection patterns of the respective first interconnection pattern and the second interconnection pattern exposed on the substrate by use of the respective first exposure management pattern and the second exposure management pattern, the third step for detecting the variation magnitude of the focus position based on the difference in interconnection width of the interconnection pattern between the first interconnection pattern and the second interconnection pattern, and the fourth step for detecting the variation magnitude of the exposure quantity based on the difference between the interconnection width of at least one interconnection pattern of the first interconnection pattern and the second interconnection pattern and the predetermined target interconnection width.
In the method for manufacturing semiconductor devices of the present invention in which exposure is performed to form an interconnection pattern of the predetermined circuit on a semiconductor substrate with correction of the exposure condition, the first exposure management pattern having interconnection patterns for exposure which are disposed with a certain interval and disposed so that the variation in the exposure quantity on the semiconductor substrate affects the interconnection width but the variation in focus position formed when the semiconductor substrate is exposed does not affect the interconnection width, and the second exposure management pattern having interconnection patterns which are disposed with a certain interval different from that of the first exposure management pattern and disposed so that both focus variation and exposure quantity variation affect the interconnection width are exposed on the semiconductor substrate. Next, the interconnection width of respective interconnection patterns of the respective first interconnection pattern and the second interconnection pattern exposed by use of the respective first exposure management pattern and the second exposure management pattern is measured. The error of the focus position is detected based on the difference in the interconnection width of respective interconnection patterns between the first interconnection pattern and the second interconnection pattern. Further, the error of the exposure quantity is detected based on the difference between the interconnection width of at least one interconnection pattern of the first interconnection pattern and the second interconnection pattern and the previously set target interconnection width. Thus, the focus position variation and sensitivity variation are detected separately without previous calculation of the correction magnitude which is optimal for exposure of an interconnection pattern with a target-sized wring width of a semiconductor device.